Board Types
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Board type guide

4-Layer Multilayer PCB

The step up from double-sided boards: two dedicated inner planes give every signal trace a clean return path, make controlled impedance practical, and free up real routing density. Here's exactly how a 4-layer board is built, what it's made of, how to lay it out well, and which IPC classes and tolerances apply.

Made in EU Manufactured in Iași, Romania (EU) — certificate of origin available on request.
What it is

Two signal layers, two dedicated planes

A 4-layer board stacks four copper layers instead of two. The standard, most-recommended arrangement is Signal – Ground – Power – Signal: the two outer layers stay easy to route and solder, while the two inner layers are solid copper planes dedicated to ground and power.

That inner ground plane sits directly under the top signal layer, which is what actually changes the board's behavior — every signal trace now has a short, direct, low-inductance return path right next to it, instead of having to share space and current with everything else on a single reference layer. That's the mechanism behind both better signal integrity and lower radiated EMI on a 4-layer board, and it's also what makes controlled impedance practical: impedance depends on a trace sitting a controlled, uniform distance above a solid reference plane, which a 2-layer board's traces-only structure can't reliably guarantee.

A less common alternative, Ground-Signal-Signal-Ground, doubles the shielding for especially noise-sensitive designs at the cost of losing the direct power-plane proximity — for most designs, Signal-Ground-Power-Signal is the better default.

L1 Signal · L2 Ground · L3 Power · L4 Signal
  • Embedded systems too dense for 2 layers
  • Industrial controllers & communications equipment
  • Automotive ECUs and sensor/control modules
  • Moderate-speed digital and mixed-signal designs
  • Any design that needs a real, controlled-impedance reference plane
How it's made

The manufacturing process, step by step

Unlike a 2-layer board, a multilayer board doesn't exist as a single panel until it's pressed. Everything up to lamination happens on separate, thin layers — which is also why inner-layer inspection matters so much: once the stack is pressed, those layers are sealed inside and can never be touched again.

1

Inner-layer imaging & etch

The ground and power layers are built first, as their own thin double-sided core: photoresist is imaged with the plane pattern, developed, and the unwanted copper is etched away.

2

Inner-layer AOI

Before anything is laminated, the etched inner core is scanned against the original CAM data for opens, shorts, nicks or copper residue — the last chance to catch a defect that lamination would otherwise seal in permanently.

3

Oxide treatment

A black/brown-oxide treatment roughens the inner copper surface at a microscopic level, so the prepreg resin can actually bond to it during pressing instead of sliding off a surface that's too smooth.

4

Layup

The inner core, sheets of prepreg (uncured resin-glass cloth) and the two outer copper foils are stacked in the correct order and held in precise X-Y registration with tooling pins before pressing.

5

Lamination

The full stack is cured under heat and pressure in a lamination press. The prepreg resin melts, flows around the inner-layer copper features, and cures — permanently bonding all four layers into one solid board.

6

Drilling

Only now — once the board is a solid mechanical unit — is it mechanically drilled. A standard through-hole passes through all four copper layers at once; reaching only some of them needs blind or buried vias, a separate, costlier option.

7

Desmear / etchback

Drilling generates enough friction heat to smear melted resin across the freshly-exposed copper inside each hole wall. Desmear removes it — and etchback slightly recesses the resin at each layer interface — so plating can make real contact with every layer's copper.

8

PTH plating

An electroless copper seed layer is deposited on the now-clean hole walls, then built up by electrolytic plating — forming the continuous barrel that electrically joins all four layers through every hole.

9

Outer-layer imaging & etch

The same image–develop–etch sequence from step 1 is repeated on the two outer copper foils, this time defining the final outer circuit pattern including the plated hole barrels.

10

Solder mask

Liquid photoimageable solder mask is applied to both outer sides, exposed and developed, leaving pads and via openings clear while protecting the rest of the copper.

11

Silk screen

Reference designators, polarity marks and other required legend text are printed on top of the solder mask.

12

Surface finish

A solderable, oxidation-resistant finish (HASL-LF, ENIG etc.) is applied to every exposed copper pad.

13

Routing

Individual boards are cut from the production panel to their final outline.

14

Electrical test — Open & Short

Every net is tested for continuity and for isolation against every other net — critically, this now has to check every relevant layer-to-layer combination, not just top-to-bottom, since an internal short to a plane would be invisible to a simple two-point check.

15

Registration check

X-ray or cross-section (microsection) inspection confirms the inner layers stayed correctly aligned to each other and to the outer layers through pressing — per IPC-TM-650 Method 2.1.1 for destructive sampling.

16

Final QC

A final optical pass on the completed outer layers, followed by dimensional and visual inspection against the fabrication drawing and the agreed IPC class, before packing.

Materials

Core, prepreg and copper

A multilayer stack is built from two different kinds of FR4 material, and the distinction matters: core is a fully-cured, pre-manufactured laminate with copper foil already bonded to both faces — this is what the inner ground/power layer is etched from. Prepreg is fiberglass cloth pre-impregnated with resin that's only partially cured — it stays semi-rigid until lamination melts and fully cures it, and it carries no copper of its own; it exists purely as the insulating, bonding layer between the core and the outer foils. Final board thickness comes out of how those core and prepreg thicknesses are combined.

Glass styleWeaveTypical resin contentWhere it's used
1080Thin~60–68%Thin dielectric gaps, fine impedance tuning
2116Medium~48–56%General-purpose prepreg, most common default
7628Thick, dense~42–48%Thicker dielectric gaps, more mechanical stiffness

Copper weight is set per layer, not just per board — inner and outer layers are often specified differently, and current-carrying capacity has to be judged separately per layer too: a trace buried between two planes dissipates heat far worse than the same trace sitting in open air on an outer layer, so identical inner and outer copper weights don't give identical current capability. For the resin system itself, multilayer boards benefit from a higher glass-transition temperature than a simple 2-layer board needs — more lamination and reflow thermal stress is put through a thicker, more complex stack, so High-Tg material (170°C+) is the safer default once you're past 2 layers, not just an upgrade option.

Design for manufacturing

Layout & DFM guidelines for 4-layer boards

Getting real value out of the extra two layers is a layout decision, not just a fabrication one.

Keep signal on the outside, planes inside — it's what actually gives every trace a nearby return path and makes the board's EMI and signal-integrity behavior predictable.
Controlled impedance is jointly set by dielectric thickness, trace width, copper thickness and the laminate's dielectric constant together — never assume trace width alone controls it.
Default to standard through-hole vias. Blind or buried vias are a real option on 4-layer, but they add a genuine cost and process step — reserve them for an actual density or fine-pitch BGA constraint.
Size inner-layer traces wider than an outer trace carrying the same current — buried copper sheds heat far less efficiently than copper exposed to air.
Place decoupling capacitors as close as physically possible to each IC's power pins, and stitch them to the planes with short, closely-spaced vias — loop inductance here is what the extra planes are supposed to buy you.
Keep anti-pad clearances around vias tight — an oversized clearance hole through a plane quietly reduces that plane's shielding and decoupling effectiveness.
Balance copper density between layers and mirror the stack-up symmetrically. An unbalanced stack bows or twists during the post-lamination cool-down — this is a real, common failure mode, not a theoretical one.
Use non-functional copper "thieving" to fill sparse areas on any given layer — it's a cheap way to protect that copper-balance symmetry without changing the electrical design.
Standards

IPC classes & quality standards

Multilayer boards are where IPC classes stop being a formality — with inner layers sealed inside the stack, the acceptance criteria that govern registration and plating are what actually decide whether a defect was ever catchable.

IPC-6012 ClassTypical useLayer registration
Class 1General consumer electronics — lowest reliability requirement—
Class 2Dedicated-service electronics — the de facto standard for most multilayer production≈ ±75 µm (3 mil)
Class 3High-reliability — aerospace, medical, industrial high-rel≈ ±50 µm (2 mil)

IPC-6012 sets the qualification/performance bar itself; IPC-A-600 is the companion visual-acceptance standard actually used to judge what was found. IPC-2221 is the generic design standard for spacing/clearance across any board type, with IPC-2222 layering rigid-board-specific rules — stack-up symmetry and warpage control among them — on top of it. Registration and plating integrity on a finished multilayer board are verified by cross-sectioning per IPC-TM-650 Method 2.1.1, the only way to directly inspect what's actually inside a sealed stack.

PCB-ELECTRA capability

Our real specs for 4-layer boards

Everything above is general industry practice. This is what we actually build, in-house, in Iași.

Board thickness0.51 – 2.4 mm
Copper weight18 / 35 / 50 / 70 µm
Glass transition (Tg)135 °C standard, 150 °C or 170 °C on request
Minimum track / isolation0.15 mm / 0.15 mm
Minimum drill0.3 mm (0.5 mm pad)
Maximum panel (4–6 layer)335 × 440 mm
Solder maskGreen, white, black, red, blue, yellow
Surface finishHASL-LF (Pb-free, RoHS compliant)
Testing100% electrical test (short circuit and open circuit, flying probe) and AOI inspection on every board

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