6-Layer Multilayer PCB
Two more layers than a 4-layer board buys real routing density and two more signal layers to work with — at the cost of tighter registration tolerances and a meaningfully more demanding build. Here's exactly how a 6-layer board is built, what's genuinely harder about it, and which IPC classes and tolerances apply.
Four signal layers, two dedicated planes
A 6-layer board typically carries four signal layers plus two plane layers, commonly arranged as Signal – Ground – Signal – Signal – Power – Signal or a similar pattern that keeps a reference plane adjacent to every signal layer. With only two plane layers to go around, one signal-to-signal interface is normally unavoidable — the fix is to keep it to exactly one, push it to the two innermost layers as shown, and route that pair orthogonally to each other (or treat them as a tightly-coupled pair) rather than letting either run long, independent single-ended traces. A second signal-to-signal interface anywhere else in the stack, or one sitting on an outer layer, is what actually breaks return-path continuity and gets flagged as the worst EMC choice at 6 layers.
The extra two layers over a 4-layer board buy real routing density, room for multiple isolated power rails, and signal layers that each sit next to at least one reference plane — at the cost of a genuinely more demanding build: more inner-layer imaging/etch/AOI cycles, tighter registration tolerance stacked across more interfaces, and a lot more layer-pair combinations to verify electrically.
- Telecom & networking infrastructure
- Industrial automation controllers
- Automotive ADAS-adjacent and Ethernet modules
- Denser embedded and mixed-signal systems
- Designs with multiple isolated power rails
The manufacturing process — and what's harder than 4-layer
A standard through-hole-only 6-layer board is still built from multiple cores and prepreg pressed in one lamination cycle — genuinely separate, sequential press cycles are reserved for designs that need blind or buried vias. What actually gets harder at 6 layers is registration, inspection volume, and electrical-test complexity.
Inner-layer imaging & etch
Now applied to two double-sided cores (four inner layers) instead of one — twice the inner-layer imaging and etching work of a 4-layer board.
Inner-layer AOI
Every inner layer is optically inspected before layup — with more layers, there are more passes and more chances to catch a defect before it becomes permanent.
Oxide treatment
Each inner core gets a black/brown-oxide treatment to roughen the copper for a reliable bond to the surrounding prepreg.
Layup
Two inner cores, prepreg sheets and outer foils are stacked in the correct sequence. Registration is more critical here than on 4-layer — there are simply more core/prepreg interfaces that all have to land in alignment.
Lamination
The full six-layer stack is cured under heat and pressure in a single press cycle, bonding every layer into one solid board.
Drilling
A standard through-hole still passes through all six layers unless blind or buried vias were specified — which become genuinely more useful at 6 layers, letting a via stop at an inner layer instead of drilling through unrelated ones.
Desmear / etchback
Resin smear is cleaned from every hole wall — with more inner-layer copper rings exposed inside each barrel, there are more interfaces that each need a clean connection.
PTH plating
Electroless and electrolytic copper plating forms the barrel connecting all six layers, now needing reliable contact across six annular rings instead of four.
Outer-layer imaging & etch
The final outer circuit pattern is imaged and etched on both outer copper foils.
Solder mask & silk screen
Applied and cured on both outer sides as standard.
Surface finish
Applied to every exposed pad for reliable, oxidation-free soldering.
Routing
Boards are cut from the production panel to their final outline.
Electrical test
The number of layer-pair and net-pair combinations to check for isolation grows fast with layer count — this step is measurably more involved than on a 4-layer board, and thicker panels need extra fixturing to prevent warp during test.
Registration check
X-ray or cross-section inspection matters even more here — cumulative misalignment risk compounds with every added layer interface, and a registration error shrinks the contact area between a via and its capture pad.
Final QC
A final optical pass on the outer layers, then dimensional and visual inspection against the drawing and agreed IPC class.
More cores, more copper balance to manage
A 6-layer stack is built from two double-sided cores (forming the four inner layers) plus prepreg and outer copper foil, combined to hit the target overall thickness. High-Tg material (170°C+) is the safer default at this layer count, not just an upgrade — lead-free reflow at 245–260°C puts real thermal stress through a thicker, more complex stack, and standard Tg material is more prone to delamination under that stress.
Copper balance matters more at 6 layers than at 4. Keeping copper coverage within roughly 10–15% between adjacent layers is the standard guidance — boards with more than ~20% imbalance between adjacent layers are meaningfully more likely to warp during lamination, and with six layers there are simply more adjacent-layer pairs where that imbalance can creep in. Non-functional copper "thieving" in sparse areas is the standard, cheap fix.
Layout & DFM guidelines for 6-layer boards
The extra layers only pay off if the stack-up and via strategy are planned deliberately.
IPC classes & quality standards
6-layer boards land in demanding end-uses often enough that Class 3 is a common, not exceptional, specification.
| IPC-6012 Class | Typical use | Layer registration |
|---|---|---|
| Class 1 | General consumer electronics | — |
| Class 2 | Dedicated-service electronics — common baseline for 6-layer | ≈ ±75 µm (3 mil) |
| Class 3 | High-reliability — telecom, industrial, aerospace — commonly specified at 6 layers | ≈ ±50 µm (2 mil) |
Class 3 also tightens minimum annular ring and plating-thickness requirements, and if the design uses blind or buried vias, those get their own class-specific fill and capture-pad rules to prevent flux entrapment and electrochemical migration. As at 4 layers, IPC-A-600 sets the visual acceptance criteria, IPC-2221/2222 govern the underlying design rules, and cross-sectioning per IPC-TM-650 Method 2.1.1 is how registration and plating quality actually get verified on a finished board.
Our real specs for 6-layer boards
Everything above is general industry practice. This is what we actually build, in-house, in Iași.
| Board thickness | 0.51 – 2.4 mm |
| Copper weight | 18 / 35 / 50 / 70 µm |
| Glass transition (Tg) | 135 °C standard, 150 °C or 170 °C on request |
| Minimum track / isolation | 0.15 mm / 0.15 mm |
| Minimum drill | 0.3 mm (0.5 mm pad) |
| Maximum panel (4–6 layer) | 335 × 440 mm |
| Solder mask | Green, white, black, red, blue, yellow |
| Surface finish | HASL-LF (Pb-free, RoHS compliant) |
| Testing | 100% electrical test (short circuit and open circuit, flying probe) and AOI inspection on every board |
Ready to price a 6-layer board?
Configure layers, dimensions and finish and get an instant quote.